Background Digital Calibration of Comparator Offsets in Pipeline ADCs

This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.Junta de Andalucía P09-TIC-5386Gobierno Español TEC2011-2830

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications

This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135

Random chopping in ΣΔ modulators

Organizado por la Universidad de Zaragoza (Unizar) del 18 al 20 de Noviembre del 2009Σ∆ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result Σ∆ modulators are often the preferred option for sensor and instrumentation. Offset and Flicker noise are usual concerns for this type of applications and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Frequency-shaped random chopping has been pro- posed to minimize the impact of reference voltage interference. It is shown in this paper that the chopper signal is not the only term that modulates the offset and Flicker noise and that unwanted crosstalk can significantly degrade the performance of the modulator.Junta de Andalucía EXC/2005/TIC-927Gobierno de España TEC-2007-6807

Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators

This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.Junta de Andalucía P09-TIC-5386Ministerio de Economía y Competitividad TEC2011-2830

On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.Gobierno de España TEC-2007-68072Consejo Superior de Investigaciones Científicas 200850I21

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm). Post-layout simulation results for a case of study with typical jitter of 68fs for a 1.8V 80dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.Gobierno de España TEC2015-68448-REuropean Space Agency 4000108445-13-NL-R

A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications

This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and centered at 2.5MHz, designed in a 90nm 2.5V 7M and MIM capacitors CMOS process technology. The filter compliants with the requirements of the IEEE802.15.4 standard. Simulation results including mismatching and process variations over the extracted view of the circuit are shown. The filter has a nominal gain of 12dB, good selectivity (20dB@2MHz offset), high image rejection (51dB nominal) and low power consumption (3.6mA @2.5V).Junta de Andalucía TIC-927Gobierno de España TEC2007-6807

Procedimiento adaptativo para la estimación de la inl en convertidores analógico-digitales (adcs).

Procedimiento adaptativo para la estimación de la INL en convertidores analógico-digitales (ADCs).Permite caracterizar y testar los convertidores analógico-digitales mediante la estimación de la No-Linealidad-Integral (Integral-Non-Linearity, INL, en ing

Procedimiento adaptativo de calibración dígital concurrente del offset en comparadores en convertidores analógico-digitales (adcs).

El objeto de la presente invención es un procedimiento adaptativo para la calibración del offset de comparadores en convertidores analógico-digitales (ADCs). La técnica que implementa permite ajustar mediante un control digital de bajo coste la tensión u

“En los bordes del archivo: escrituras periféricas, escrituras efímeras en los Virreinatos de Indias”

En los bordes del archivo es el sitio web de "En los bordes del archivo: escrituras periféricas, escrituras efímeras en los Virreinatos de Indias”, proyecto coordinado entre dos equipos de investigación de la Universidad Complutense de Madrid (UCM) y del Consejo Superior de Investigaciones Científicas (CSIC).© En los bordes del archivo - 2017. Algunos derechos reservados. Licencia Creative Commons.. Consulta realizada en 2019-03-22.La finalidad que orienta el Proyecto Coordinado “En los bordes del archivo: escrituras periféricas, escrituras efímeras en los Virreinatos de Indias” queda definida en la voz que encabeza su título, estudiada en relación con la escritura hispanoamericana colonial y abordada desde una comprensión amplia del término, no sólo en su sentido más positivista, en tanto acumulación o repositorio de documentos para la conformación de la verdad historiográfica y la imposición del poder imperial, sino en las acepciones paralelas de “lugar de la memoria” y de “metáfora epistémica”, de herramienta que permite la interpretación “arqueológica” de los saberes.Peer reviewe